The design was elaborated using VHDL and implemented into logic blocks using SPARTAN S05PC84-4. ... Table 3 shows the delay and area required by the hardware implementation of the modified Booth multiplier which uses a Wallaceanbsp;...
|Title||:||Computer and Information Sciences -- ISCIS 2003|
|Author||:||Adnan Yazici, Cevat Sener|
|Publisher||:||Springer - 2003-10-24|