Increasing on-chip wire delay and growing off-chip miss latency, present two key challenges in designing large Level-2 (L2) CMP caches. Currently, some CMPs use a shared L2 cache to maximize cache capacity and minimize off-chip misses. Others use private L2 caches, replicating data to limit the delay from slow on-chip wires and minimize cache access time. Ideally, to improve performance for a wide variety of workloads, CMPs prefer both the capacity of a shared cache and the access latency of private caches.In comparison, the 64-banked Shared CMP-TLC design required l6 8-byte wide links to connect with its more distributed 64-banked shared ... Furthermore, the maximum distance between Private CMP-TLCa#39;s L2 cache tags and the center switches is shorter ... L1 Dl Private ^U- Private L1 \Ap CPU 3 *^Mqi CPU 4 L1 |f L2 L2 L1anbsp;...
|Title||:||Managing wire delay in chip multiprocessor caches|
|Author||:||Bradford M. Beckmann, The University of Wisconsin - Madison|