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More importantly, the inverter, defined over GF(24)3, can be realized with 2.7 k gates with a critical path of 3 ns. Synthesis Results. The 85-error correcting [2720, 2550] RS code, designed for a 43Gb/s system, was synthesized with Synopsysa#39; Design Analyzer tool. ... x [255, 239] RS decoders, implemented in Fujitsua#39;s CS91 0.11/im CMOS at 1.2V for a 43Gb/s system, that has a layout size of 4.9 x 2.3 mm2, anbsp;...

Author:Electron Devices, Yugoslavia IEEE Section. ED/SSC Chapter, IEEE Solid-State Circuits Society, Yugoslavia IEEE Section. Electron Devices Chapter
Publisher:IEEE - 1995


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