Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.The use of special cooling equipment to remove the heat during wafer probing is difficult and costly due to the ... (ii) Manufacturing yield loss can be caused by the power/groun d noise and/or the voltage (IR) drop. ... The voltage drop problem is important in the deep-submicron era due to the increased current and wire resistance, and ... For example at 1.2 V supply, a 0.6 A current flowing through 0.4 ohm resistance will cause a voltage drop of 0.24 V which is 20% of the supply voltage.
|Title||:||Power-Constrained Testing of VLSI Circuits|
|Author||:||Nicola Nicolici, Bashir M. Al-Hashimi|
|Publisher||:||Springer Science & Business Media - 2003-02-28|