RAPID PROTOTYPING AND PERFORMANCE EVALUATION OF RECODED MULTIPLIERS USING FPGAs A CUSTOMER-ORIENTED TEST - ESTIMATION TEST Hede Ma Dept. of ... They were suggested by Booth , later improved by MacSorley  (Modified Bootha#39;s algorithm). ... The design and the VHDL code are optimized in order to obtain the best result in terms of speed and number of gates used.
|Author||:||Florida International University. Dept. of Electrical and Computer Engineering, University of Miami. Dept. of Electrical and Computer Engineering, Institute of Electrical and Electronics Engineers. Miami Section, Institute of Electrical and Electronics Engineers. Region 3|
|Publisher||:||Institute of Electrical & Electronics Engineers(IEEE) - 1994-04|